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1 ? fn9198.4 isl97650 4-channel integrated lcd supply the isl97650 represents a high power, integrated lcd supply ic targeted at large panel lcd displays. the isl97650 integrates a high power, 2.6a boost converter for a vdd generation, an integrated v on charge pump, a v off charge pump driver, v on slicing circuitry and a buck regulator with 2a switch for logic generation. the isl97650 has been designed for ease of layout and low bom cost. supply sequencing is integrated for both a vdd -> v off -> v on and a vdd /v off -> v on sequences. the tft power sequence uses a separate enable to the logic buck regulator for maximum flexibility. peak efficiencies are >90% for both the boost and buck while operating from a 4v to 14v input supply. the current mode buck offers superior line and load regulation. available in the 36 ld tqfn package, the isl9765 0 is specified for ambient operation over the -40c to +105c temperature range. pinout isl97650 (36 ld tqfn) top view features ? 4v to 14v input supply ?a vdd boost up to 20v, with integrated 2.8a fet ? integrated v on charge pump, up to 35v out ?v off charge pump driver, down to -18v ?v logic buck down to 1.2v, wi th integrated 2a fet ? automatic start-up sequencing -a vdd -> v off -> v on or a vdd /v off -> v on - independent logic enable ?v on slicing ? thermally enhanced 6x6 thin qfn package ? pb-free (rohs compliant) applications ? lcd monitors (15?+) ? lcd-tvs (up to 40?) ? notebook displays (up to 16?) ? industrial/medical lcd displays thermal pad 27 26 25 24 23 22 21 36 35 34 33 32 10 11 12 13 14 1 2 3 4 5 6 7 lx1 lx2 cb lxl nc vsup fbl agnd1 pgnd1 pgnd2 vinl nout pgnd3 fbn vdc2 en fbb vin cm1 agnd2 drn com pout c1- 8 9 20 19 15 31 16 30 vref fbp c1+ c2- cm2 ctl delb enl 17 18 c2+ nc 29 28 cdel vdc1 ordering information part number (note) part marking package (pb-free) pkg. dwg. # isl97650artz-t* isl976 50artz 36 ld 6x6 thin tqfn l36.6x6 isl97650artz-tk* isl976 50artz 36 ld 6x6 thin tqfn l36.6x6 *please refer to tb347 for details on reel specifications note: intersil pb-free plus anneal products employ special pb-free material sets; molding compounds/die attach materials and 100% matte tin plate termination finish, which are rohs compliant and compatible with both snpb and pb-free soldering operations. intersil pb-free products are msl classi fied at pb-free peak reflow temperatures that meet or exceed the pb-free requirements of ipc/jedec j std-020. data sheet april 17, 2009 caution: these devices are sensitive to electrosta tic discharge; follow proper ic handling procedures. 1-888-intersil or 1-888-468-3774 | intersil (and design) is a registered trademark of intersil americas inc. copyright intersil americas inc. 2006, 2009. all rights reserved all other trademarks mentioned are the property of their respective owners.
2 fn9198.4 april 17, 2009 absolute maxi mum ratings (t a = +25c) thermal information maximum pin voltages, all pins except below . . . . . . . . . . . . . . 6.5v lx1, lx2, vsup, nout, delb, c2- . . . . . . . . . . . . . . . . . . . .24v c1- . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14v vin1, vinl . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16.5v drn, com, pout, c1+, c2+ . . . . . . . . . . . . . . . . . . . . . . . . .36v cb . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21v recommended operating conditions input voltage range, vin . . . . . . . . . . . . . . . . . . . . . . . . 4v to 14v boost output voltage range, a vdd . . . . . . . . . . . . . . . . . . . . +20v v on output range, v on . . . . . . . . . . . . . . . . . . . . . . +15v to +32v v off output range, v off . . . . . . . . . . . . . . . . . . . . . . . -15v to -5v logic output voltage range, v logic . . . . . . . . . . . . +1.5v to +3.3v input capacitance, c in . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2x10f boost inductor, l1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.3h-10h output capacitance, c out . . . . . . . . . . . . . . . . . . . . . . . . . . 2x22f buck inductor, l2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3.3h to10h operating ambient temperature range . . . . . . . . -40c to +105c operating junction temperature . . . . . . . . . . . . . . -40c to +125c thermal resistance ja (c/w) jc (c/w) 6x6 qfn package (notes 1, 2) . . . . . . 30 2.5 maximum junction temperature (plastic package) . . . . . . . +150c maximum storage temperature range . . . . . . . . . .-65c to +150c power dissipation t a + 25c . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3.3w t a = +70c. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1.8w t a = +85c. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1.3w t a = +100c. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .0.8w pb-free reflow profile. . . . . . . . . . . . . . . . . . . . . . . . .see link below http://www.intersil.com/pbfree/pb-freereflow.asp caution: do not operate at or near the maximum ratings listed fo r extended periods of time. exposure to such conditions may adv ersely impact product reliability and result in failures not covered by warranty. notes: 1. ja is measured in free air with the component mounted on a high ef fective thermal conductivity te st board with ?direct attach? fe atures. see tech brief tb379. 2. for jc , the ?case temp? location is the center of the exposed metal pad on the package underside. electrical specifications v in = 12v, v boost = v sup = 15v, v on = 25v, v off = -8v, over-temperature from -40c to +105c, unless otherwise stated. parameters with min and/or max limits are 100% tested at +25c, unless otherwise specified. temperature limits established by characterization and are not production tested. parameter description conditions min typ max unit supply pins v in supply voltage (vin1) 4 12 14 v v inl logic supply voltage 4 12 14 v v sup charge pumps and v on slice positive supply 420v i vin quiescent current into v in enabled, no switching 3 5 ma disabled 25 50 a i inl logic supply current enabled, no switching 0.25 2 ma disabled 1 25 a i sup v sup supply current enabled, no switching and vpout = v sup 1ma disabled 1 10 a vlor undervoltage lockout threshold v dc rising 3.85 4 v vlof undervoltage lockout threshold v dc falling 3.3 3.45 v v ref reference voltage t a = +25c 1.18 1.205 1.225 v 1.177 1.205 1.228 v f osc oscillator frequency 1020 1200 1380 khz a vdd boost d min minimum duty cycle 20 25 % d max maximum duty cycle 84 % isl97650
3 fn9198.4 april 17, 2009 v boost boost output range 1.25 *v in 20 v i boost boost switch current current limit 2.6 3.2 3.8 a eff boost peak efficiency see graphs and component recommendations 90+ % r ds(on) switch on resistance 160 300 m v boost / v in line regulation 5v < v in < 13v 0.4 1.0 %/v v boost / i out load regulation 100ma < load < 200ma 0.1 0.5 % v fbb boost feedback voltage t a = +25c 1.192 1.205 1.218 v 1.188 1.205 1.222 v acc boost a vdd output accuracy t a = +25c -1.5 1.5 % tss soft-start period for a vdd c del = 220nf 9.6 ms v logic buck v buck buck output voltage output current = 0.5a 1.5 5.5 v i buck buck switch current current limit 2.0 2.4 2.9 a eff buck peak efficiency see graphs and component recommendations 92 % r ds-onbk switch on-resistance 200 400 m v buck / v in line regulation 5v < v in < 13v 0.1 1.0 %/v v buck / i out load regulation 100ma < load < 500ma 0.2 1 % v fbl fbl regulation voltage t a = +25c 1.176 1.2 1.224 v 1.174 1.2 1.226 v acc logic v logic output accuracy t a = +25c -2 2 % tss l soft-start period for v(logic) c(vref) = 220nf (note - no soft-start if en asserted high before enb) 0.5 ms negative (v off ) charge pump v off v off output voltage range 2x charge pump -v sup +1.4v 0v iload_ncp_min external load driving capability v sup > 5v 30 ma ron(nout)h high-side driv er on-resistance at n out i(nout) = +60ma 10 ron(nout)l low-side driver on-resistance at n out i(nout) = -60ma 5 ipu(nout)lim pull-up current limit in n out v(nout) = 0v to v(sup)-0.5v 60 270 ma ipd(nout)lim pull-down current limit in n out v(nout) = 0.36v to v(vsup) -200 -60 ma i(nout)leak leakage current in n out v(fbn) < 0 or en = low -5 5 a v fbn fbn regulation voltage t a = +25c 0.173 0.203 0.233 v 0.171 0.203 0.235 v accn v off output accuracy ioff = 1ma, t a = +25c -3 +3 % d_ncp_max max duty cycle of the negative charge pump 50 % rpd(fbn)off pull-down resistance, not active i(fbn) = 500a 1.5 3.3 5.5 k electrical specifications v in = 12v, v boost = v sup = 15v, v on = 25v, v off = -8v, over-temperature from -40c to +105c, unless otherwise stated. parameters with min and/or max limits are 100% tested at +25c, unless otherwise specified. temperature limits established by characterization and are not production tested. (continued) parameter description conditions min typ max unit isl97650
4 fn9198.4 april 17, 2009 positive (v on ) charge pump v on v on output voltage range 2x or 3x charge pump vsup+ 2v 34 v iload_pcp_min external load driving capability v on = 25v (2x charge pump) 20 ma v on = 34v (3x charge pump) 20 ma ron(vsup_sw) on resistance of v sup input switch i(switch) = +40ma 10 17 ron(c1/2-)h high-side dr iver on-resistance at c1- and c2- i(c1/2-) = +40ma 30 ron(c1/2-)l low-side driver on-resistance at c1- and c2- i(c1/2-) = -40ma 4 7 ipu(vsup_sw) pull-up current limit in v sup input switch v(c2+) = 0v to v(sup) - 0.4v - v(diode) 40 100 ma ipu(c1/2-) pull-up current limit in c1- and c2- v(c1/2-) = 0v to v(vsup) - 0.4v 40 100 ma ipd(c1/2-) pull-down current limit in c1- and c2- v(c1/2-) = 0.2v to v(vsup) -100 -40 ma i(pout)leak leakage current in p out en = low -5 5 a v fbp fbp regulation voltage t a = +25c 1.176 1.2 1.224 v 1.172 1.2 1.228 v accp v on output accuracy i on = 1ma, t a = +25c -2 +2 % d_pcp_max max duty cycle of the positive charge pump 50 % v(diode) internal schottky diode forward voltage i(diode) = +40ma 700 800 mv enable inputs vhi-en enable ?high? 2.2 v vlo_en enable ?low? 0.8 v ien_pd enable pin pull-down current v en > vlo_en 25 a vhi-enl logic enable ?high? 2.2 v vlo-enl logic enable ?low? 0.8 v ienl_pd logic enable pin pull-down current v enl > vlo_enl 25 a v on slice positive supply = v(pout) i(pout)_slice v on slice current from p out supply ctl = vdd, sequence complete 200 400 a ctl = agnd, sequence complete 100 150 a ron(pout-com) on-resistance between p out - com ctl = vdd, sequence complete 5 10 ron(drn-com) on-resistance between drn - com ctl = acgnd, sequence complete 30 60 ron_com on-resistance between com and pgnd3 200 500 1500 vlo ctl input low voltage 0.8 v vhi ctl input high voltage 2.2 v fault detection thresholds t_off thermal shut-down (latched and reset by power cycle or en cycle) temperature rising 150 c vth_a vdd (fbb) a vdd boost short detection v(fbb) falling less than 0.9 v electrical specifications v in = 12v, v boost = v sup = 15v, v on = 25v, v off = -8v, over-temperature from -40c to +105c, unless otherwise stated. parameters with min and/or max limits are 100% tested at +25c, unless otherwise specified. temperature limits established by characterization and are not production tested. (continued) parameter description conditions min typ max unit isl97650
5 fn9198.4 april 17, 2009 vth_v logic (fbl) v logic buck short detection v(fbl) falling less than 0.9 v vth_pout(fbp) p out charge pump short detection v(fbp) falling less than 0.9 v vth_nout(fbn) n out charge pump short detection v(fbn) rising more than 0.4 v t fd fault delay time to chip turns off 52 ms start-up sequencing t start-up enable to a vdd start time c del = 220nf 80 ms i delb_on delb pull-down current or resistance when enabled by the start-up sequence vdelb > 0.9v 36 50 70 a vdelb < 0.9v 1.00 1.326 1.75 k i delb_off delb pull-down current or resistance when disabled vdelb < 20v 500 na c del sequence timing and fault time out capacitor 10 220 nf t voff a vdd to v off c del = 220nf 9 ms t von v off to v on delay c del = 220nf 20 ms t von-slice v on to v on-slice delay c del = 220nf 17 ms electrical specifications v in = 12v, v boost = v sup = 15v, v on = 25v, v off = -8v, over-temperature from -40c to +105c, unless otherwise stated. parameters with min and/or max limits are 100% tested at +25c, unless otherwise specified. temperature limits established by characterization and are not production tested. (continued) parameter description conditions min typ max unit typical performance curves figure 1. boost efficiency figure 2. boost load regulation efficiency (%) 0 20 40 60 80 100 0 500 1000 1500 i o (ma) v in = 12v v in = 5v v in = 12v v in = 5v 0 0.02 0.04 0.06 0.08 0.10 0.12 0 500 1000 1500 2000 i o (ma) load regulation (%) isl97650
6 fn9198.4 april 17, 2009 figure 3. buck efficiency figure 4. buck load regulation figure 5. v off load regulation vs i off figure 6. v on load regulation vs i on figure 7. boost discontinuous mode figure 8. threshold of boost from dc to cc mode typical performance curves (continued) v in = 12v v in = 5v 0 0 500 1000 1500 2000 i o (ma) 20 40 60 80 100 efficiency (%) v in = 12v v in = 5v 0 500 1000 1500 2000 i o (ma) -2.0 -1.5 -1.0 -0.5 0 load regulation (%) -0.7 -0.6 -0.5 -0.4 -0.3 -0.2 -0.1 0 0 1020304050607080 i off (ma) v off load regulation (%) v off = -8v -0.35 -0.30 -0.20 -0.15 -0.10 -0.05 0 0 102030405060 i on (ma) v on load regulation (%) v on = 25v -0.25 200ns/div ch1 = lx(boost)(5v/div) ch2 = io(boost)(10ma/div) 200ns/div ch1 = lx(boost)(5v/div) ch 2 = io(boost)(10ma/div) isl97650
7 fn9198.4 april 17, 2009 figure 9. buck discontinuous mode figure 10. threshold of buck from dc to cc mode figure 11. boost converter pulse-skipping mode waveform figure 12. transient response of boost figure 13. transient response of buck figure 14. start-up sequence typical performance curves (continued) 400ns/div ch1 = lx(buck)(5v/div) ch2 = io(buck)(10ma/div) 400ns/div ch1 = lx(buck)(5v/div) ch2 = io(buck)(10ma/div) ch1 = v in ch2 = lx, ch3 = a vdd, ch4 = i inductor 1ms/div ch1 = a vdd (v boost )(100mv/div) ch2 = io(boost)(100ma/div) 1ms/div ch1 = v logic (v buck )(10mv/div) ch2 = io(buck)(100ma/div) ch1 = c dly , ch2 = v ref , ch3 = v logic, ch4 = v on r1 = a vdd , r2 = a vdd_delay , r3 = v off isl97650
8 fn9198.4 april 17, 2009 pin descriptions pin number pin name description 1 lx1 internal boost switch connection 2 lx2 internal boost switch connection 3 cb logic buck, boost strap pin 4 lxl buck converter output 5, 18 nc no connect. connect to die pad a nd gnd for improved thermal efficiency. 6 vsup positive supply for charge pumps 7 fbl logic buck feedback pin 8 cm2 buck compensation network pin 9 ctl input control for v on slice output 10 agnd2 signal gnd pin 11 drn lower reference voltage for v on slice output 12 com v on slice output: when ctl = 1, com is connected to src through a 5 resistor; when ctl = 0, com is connected to drn through a 30 resistor 13 pout positive charge pump out 14 c1- charge pump capacitor 1, negative connection 15 c1+ charge pump capacitor 1, positive connection 16 c2- charge pump capacitor 2, negative connection 17 c2+ charge pump capacitor 2, positive connection 19 fbp positive charge pump feedback pin 20 vref reference voltage 21 fbn negative charge pump feedback pin 22 pgnd3 power ground for v off , v on and v on slice 23 nout negative charge pump output 24 vinl logic buck supply voltage 25, 26 pgnd2, 1 boost power grounds 27 agnd1 signal ground pin 28 vdc1 internal suppl y decoupling capacitor 29 cdel delay capacitor for start up sequenci ng, soft-start and fault detection timers 30 enl buck enable for v logic output 31 delb open drain nfet output to drive optional a vdd delay pfet 32 cm1 boost compensation network pin 33 vin input voltage pin 34 fbb boost feedback pin 35 en enable for boost, charge pumps and v on slice (independent of enl) 36 vdc2 internal suppl y decoupling capacitor exposed die plate n/a connect expos ed die plate on rear of package to acgnd and the pgnd1, 2 pins. see the section on "?layout recommendation? on page 19" for pcb layout thermal considerations. isl97650
9 fn9198.4 april 17, 2009 block diagram + - + - + - + - + - + - + - + - + - control logic sawtooth generator current amplifier current limit comparator current limit threshold reference bias and sequence controller v ref gm amplifier uvlo comparator 1.2mhz oscillator 0.75 v ref regulator v sup 0.2v uvlo comparator 0.4v 0.75 v ref v ref p out r sense buffer regulator control logic v ref sawtooth generator 0.75 v ref uvlo comparator slope compensation gm amplifier sup current limit threshold current limit comparator sup c1- c1+ c2+ c2- p out driv ctl com buffer lx1 pgnd1 vdc2 cb lxl cm2 fbl fbp fbn n out v in2 enl cdel en v in1 , v in2 vdc1 fbb cm1 pgnd2 lx2 current amplifier slope compensation v ref delb isl97650
10 fn9198.4 april 17, 2009 typical application diagram c1+ v on slice fbl lxl nout fbn cm1 cdel en p out boost v off cp v on cp buck vin cm2 enl agnd pgnd1 cb vinl fbp v ref v sup fbb lx2 lx1 v off v on v logic com drn ctl v on slice c1- c2+ c2- bias and sequence control delb pgnd2 pgnd3 a vdd_delay a vdd v in to gate driver ic 4.7nf c3 10k r1 6.8f l1 d1 20f c2 55k r3 5k r5 open c4 300k r4 1f c5 15v 0.22f c6 220nf c7 220nf c8 10f c10 10k r2 4.7nf c9 40k r6 820p c20 328k r7 220nf c12 d2 d3 -8v 470nf c13 983k r8 470nf c14 +25v 50k r9 1k r11 r12 0.1f c15 100k r13 1f c16 l2 6.8h d4 2k r14 20f c17 3.3v r15 1.2k vdc2 0.47f c17 vdc2 0.47f c18 vdc1 0.47f c18 r16* c18* 100p c19 100p c21 2.2nf c22 *open component positions 220nf c11 2.2f c1 4.7 r18 500k r20 r10 68k isl97650
11 fn9198.4 april 17, 2009 applications information the isl97650 provides a complete power solution for tft lcd applications. the system consists of one boost converter to generate a vdd voltage for column drivers, one buck converter to provide voltage to logic circuit in the lcd panel, one integrated v on charge pump and one v off linear-regulator controller to provide the voltage to row drivers. this part also integrates v on -slice circuit which can help to optimize the picture quality. with the high output current capability, this part is ideal for big screen lcd tv and monitor panel application. the integrated boost converter and buck converter operate at 1.2mhz which can allow to use multilayer ceramic capacitors and low profile inductor which result in low cost, compact and reliable system. t he logic output voltage is independently enabled to give flexibility to the system designers. boost converter the boost converter is a current mode pwm converter operating at a fixed frequency of 1.2mhz. it can operate in both discontinuous conduction mode (dcm) at light load and continuous mode (ccm). in continuous current mode, current flows continuously in the inductor during the entire switching cycle in steady st ate operation. the voltage conversion ratio in continuous current mode is given by equation 1: where d is the duty cycle of the switching mosfet. the boost converter uses a summ ing amplifier architecture consisting of gm stages for voltage feedback, current feedback and slope compensatio n. a comparator looks at the peak inductor current cycle by cycle and terminates the pwm cycle if the current limit is reached. an external resistor divider is required to divide the output voltage down to the nominal reference voltage. current drawn by the resistor network should be limited to maintain the overall converter efficiency. the maximum value of the resistor network is limited by the feedback input bias current and the potential for noise being coupled into the feedback pin. a resistor network in the order of 60k is recommended. the boost converter output voltage is determined by equation 2: the current through the mosfet is limited to 2.6apeak. this restricts the maximum out put current (average) based on equation 3: where il is peak to peak inductor ripple current, and is set by equation 4: where f s is the switching frequency(1.2mhz). table 1 gives typical values (m argins are considered 10%, 3%, 20%, 10% and 15% on v in , v o , l, fs and i omax ): the minimum duty cycle of the isl97650 is 25%. when the operating duty cycle is lower than the minimum duty cycle, the part will not switch in some cycles randomly, which will cause some lx pulses to be skipped. in this case, lx pulses are not consistent any more, but the output voltage (a vdd ) is still regulated by the ratio of r3 and r5. this relationship is given by equation 2. because some lx pulses are skipped, the ripple current in the inductor will become bigger. under the worst case, the ripple cu rrent will be from 0 to the threshold of the current limit. in turn, the bigger ripple current will increase the output voltag e ripple. hence, it will need more output capacitors to keep th e output ripple at the same level. when the input voltage equ als, or is larger than, the output voltage, the boost converter will stop switching. the boost converter is not regulated any more, but the part will still be on and other channels are still regulated. the typical waveforms of pulse-skipping mode are shown in the section ?typical performance curves? on page 5. boost converter input capacitor an input capacitor is used to suppress the voltage ripple injected into the boost converte r. the ceramic capacitor with capacitance larger than 10f is recommended. the voltage rating of input capacitor shoul d be larger than the maximum input voltage. some capacitors are recommended in table 2 for input capacitor. v boost v in ------------------ 1 1d ? ------------- = (eq. 1) a vdd r 3 r 5 + r 5 -------------------- - v fbb = (eq. 2) i omax i lmt i l 2 -------- ? ?? ?? v in v o --------- = (eq. 3) table 1. maximum output current calculation v in (v) v o (v) l (h) f s (mhz) i omax (ma) 5 9 6.8 1.2 1138 5 12 6.8 1.2 777 4 15 6.8 1.2 560 12 15 6.8 1.2 1345 12 18 6.8 1.2 998 table 2. boost converter input capacitor recommendation capacitor size vendor part number 10f/25v 1210 tdk c3225x7r1e106m 10f/25v 1210 murata grm32dr61e106k --------- d f s ---- - = (eq. 4) isl97650
12 fn9198.4 april 17, 2009 boost inductor the boost inductor is a critical part which influences the output voltage ripple, transient response, and efficiency. values of 3.3h to 10h are to match the internal slope compensation. the inductor must be able to handle the following average and peak current: some inductors are recommended in table 3. rectifier diode (boost converter) a high-speed diode is necessary due to the high switching frequency. schottky diodes are recommended because of their fast recovery time and low forward voltage. the reverse voltage rating of this diode should be higher than the maximum output voltage. the re ctifier diode must meet the output current and peak inductor current requirements. table 4 is some recommendations for boost converter diode. output capacitor the output capacitor supplies the load directly and reduces the ripple voltage at the output. output ripple voltage consists of two components: the voltage drop due to the inductor ripple current flowing through the esr of output capacitor, and the charging an d discharging of the output capacitor. for low esr ceramic capacitors, the output ripple is dominated by the charging and discharging of the output capacitor. the voltage rating of the output capacitor should be greater than the maximum output voltage. note: capacitors have a voltage coefficient that makes their effective capacitance drop as the voltage across then increases. c out in equation 7 assumes the effective value of the capacitor at a particular voltage and not the manufacturer's stated val ue, measured at zero volts. table 5 shows some selections of output capacitors. pi loop compensation (boost converter) the boost converter of isl97650 can be compensated by a rc network connected from cm1 pin to ground. c3 = 4.7nf and r1 = 10k rc network is used in the demo board. a higher resistor value can be used to lower the transient overshoot - however, this may be at the expense of stability to the loop. the stability can be examined by repeatedly changing the load between 100ma and a max level that is likely to be used in the system being used. the a vdd voltage should be examined with an oscilloscope set to ac 100mv/div and the amount of ringing observed when the load current changes. reduce excessive ringing by reducing the value of the resistor in series with the cm1 pin capacitor. boost converter feedback resistors and capacitor an rc network across feedback resistor r5 may be required to optimize boost stability when a vdd voltage is set to less than 12v. this network reduces the internal voltage feedback used by the ic. this rc network sets a pole in the control loop. this pole is set to approximately fp = 10khz for c out = 10f and fp = 4khz for c out = 30f. alternatively, adding a small capacitor (20 to 100pf) in parallel with r5 (i.e. r16 = short) may help to reduce a vdd noise and improve regulation, particularly if high value feedback resistors are used. table 3. boost inductor recommendation inductor dimensions (mm) vendor part number 6.8h/ 3a peak 7.3x6.8x3.2 tdk rlf7030t-6r8n3r0 6.8h/ 2.9a peak 7.6x7.6x3.0 sumida cdr7d28mnnp-6r8nc 5.2h/ 4.55a peak 10x10.1x3.8 cooper bussmann cd1-5r2 table 4. boost converter rectifier diode recommendation diode v r /i avg rating package vendor ss23 30v/2a smb fairchild semiconductor sl23 30v/2a smb vishay semiconductor i lavg i o 1d ? ------------- = (eq. 5) i lpk i lavg i l 2 -------- + = (eq. 6) v ripple i lpk esr v o v in ? v o ----------------------- - i o c out --------------- - 1 f s ---- + = (eq. 7) table 5. boost output capacitor recommendation capacitor size vendor part number 10f/25v 1210 tdk c3225x7r1e106m 10f/25v 1210 murata grm32dr61e106k r16 1 0.1 r5 -------------------------- ?? ?? 1 r3 ------- - ? ?? ?? 1 ? = (eq. 8) c18 1 2 3.142 fp r5 () ------------------------------------------------------- = (eq. 9) isl97650
13 fn9198.4 april 17, 2009 cascaded mosfet application an 20v n-channel mosfet is integrated in the boost regulator. for the applications where the output voltage is greater than 20v, an external cascaded mosfet is needed as shown in figure 15. the voltage rating of the external mosfet should be greater than a vdd . buck converter the buck converter is the step down converter, which supplies the current to the lo gic circuit of the lcd system. the isl97650 integrates an 20v n-channel mosfet to save cost and reduce external component count. in the continuous current mode, the relationship between input voltage and output voltage is as shown in equation 10: where d is the duty cycle of the switching mosfet. because d is always less than 1, the output voltage of buck converter is lower than input voltage. the peak current limit of buck converter is set to 2a, which restricts the maximum output current (average) based on equation 11: where i pp is the ripple current in the buck inductor as equation 12, where l is the buck inductor, f s is the switching frequency (1.2mhz). feedback resistors the buck converter output voltage is determined by the equation 13: where r14 and r15 are the feedback resistors of buck converter to set the output voltage. current drawn by the resistor network should be limited to maintain the overall converter efficiency. the maximum value of the resistor network is limited by the feedback input bias current and the potential for noise being coupled into the feedback pin. a resistor network in the order of 1k is recommended. buck converter input capacitor the capacitor should support the maximum ac rms current which happens when d = 0.5 and maximum output current. where i o is the output current of the buck converter. table 6 shows some recommendations for input capacitors. buck inductor an 3.3h to 10h inductor is the good choice for the buck converter. besides the inductance, the dc resistance and the saturation current are also the factor needed to be considered when choosing buck inductor. low dc resistance can help maintain high efficiency, and the saturation current rating should be 2a. here are some recommendations for buck inductor. figure 15. cascaded mosfet topology for high output voltage applications intersil isl97650 lx1, lx2 fbb a vdd v in v logic v in --------------------- - d = (eq. 10) i omax 2a i pp ? = (eq. 11) i pp v logic lf s ? --------------------- - 1d ? () ? = (eq. 12) table 6. input capacitor (buck) recommendation capacitor size vendor part number 10f/16v 1206 tdk c3216x7r1c106m 10f/10v 0805 murata grm21br61a106k 22f/16v 1210 murata c3225x7r1c226m table 7. buck inductor recommendation inductor dimensions (mm) vendor part number 4.7h/ 2.7a peak 5.7x5.0x4.7 murata lqh55dn4r7m01k 6.8h/ 3a peak 7.3x6.8x3.2 tdk rlf7030t-6r8m2r8 10h/ 2.4a peak 12.95x9.4x3.0 coilcraft do3308p-103 v logic r 14 r 15 + r 15 -------------------------- - v fbl = (eq. 13) i acrms c in () d1d ? () ? i o ? = (eq. 14) isl97650
14 fn9198.4 april 17, 2009 rectifier diode (buck converter) a schottky diode is recommended due to fast recovery and low forward voltage. the reverse voltage rating should be higher than the maximum input voltage. the peak current rating is 2a, and the average current should be as shown in equation 15: where i o is the output current of buck converter. table 8 shows some recommended diodes. output capacitor (buck converter) four 10f or two 22f ceramic capacitors are recommended for this part. the overshoot and undershoot will be reduced with more capacitance, but the recovery time will be longer. pi loop compensation (buck converter) the buck converter of isl97650 can be compensated by a rc network connected from cm2 pin to ground. c9 = 4.7nf and r2 = 2k rc network is used in the demo board. the larger value resistor can lower the transient overshoot, however, at the expense of stability of the loop. the stability can be optimized in a similar manner to that described in the section ?pi loop compensation (boost converter)? on page 12. bootstrap capacitor (c16) this capacitor is used to provid e the supply to the high driver circuitry for the buck mosfet . the bootstrap supply is formed by an internal diode and capacitor combination. a 1f is recommended for isl97650. a low value capacitor can lead to overcharging and in turn damage the part. if the load is too light, the on-time of the low side diode may be insufficient to replenish the bootstrap capacitor voltage. in this case, if v in -v buck < 1.5v, the internal mosfet pull-up device may be unable to turn-on until v logic falls. hence, there is a minimum load requirement in this case. the minimum load can be adjusted by the feedback resistors to fbl. the bootstrap capacitor can only be charged when the higher side mosfet is off. if the load is too light which can not make the on time of the low side diode be sufficient to replenish the boot strap capacitor, the mosfet can?t turn on. hence there is minimum load requirement to charge the bootstrap capacitor properly. charge pump controllers (v on and v off ) the isl97650 includes 2 independent charge pumps (see charge pump block and connection diagram, figure 17). the negative charge pump inverts the v sup voltage and provides a regulated negative output voltage. the positive charge pump doubles or triples the v sup voltage and provides a regulated positive outp ut voltage. the regulation of both the negative and positive charge pumps is generated by internal comparator that senses the output voltage and compares it with the internal reference. the pumps use pulse width modulation to adjust the pump period, depending on the load present. the pumps can provide 30ma for v off and 20ma for v on . positive charge pump design consideration the positive charge pump integrat es all the diodes (d1, d2 and d3 shown in the ?block diagram? on page 9) required for x2 (v sup doubler) and x3 (v sup tripler) modes of operation. during the chip start-up sequence, the mode of operation is automatically detec ted when the charge pump is enabled. with both c7 and c8 present, the x3 mode of operation is detected. with c7 present, c8 open and with c1+ shorted to c2+, the x2 mode of operation will be detected. due to the internal switches to v sup (m1, m2 and m3), p out is independent of the voltage on v sup until the charge pump is enabled. this is important for tft applications where the negative charge pump output voltage (v off ) and a vdd supplies need to be established before p out . the maximum p out charge pump current can be estimated from the following equations assuming a 50% switching duty: note: v diode (2 ? i max ) is the on-chip diode voltage as a function of i max and v diode (40ma) < 0.7v. table 8. buck rectifier diode recommendation diode v r /i avg rating package vendor pmeg2020ej 20v/2a sod323f philips semiconductors ss22 20v/2a smb fairchild semiconductor table 9. buck output capacitor recommendation capacitor size vendor part number 10f/6.3v 0805 tdk c2012x5r0j106m 10f/6.3v 0805 murata grm21br60j106k 22f/6.3v 1210 tdk c3216x5r0j226m 100f/6.3v 1206 murata grm31cr60j107m i avg 1d ? () *i o = (eq. 15) i max 2x () min of 50ma or 2v ? sup 2 ? v diode 2i max ? () vv on () ? ? 22r onh r onl + ? () ? () ---------------------------------------------------------------------------------------------------------------------- 0.95a ? i max 3x () min of 50ma or 3v ? sup 3 ? v diode 2i max ? () vv on () ? ? 23r onh 2r ? onl + ? () ? () ---------------------------------------------------------------------------------------------------------------------- 0.95v ? (eq. 16) isl97650
15 fn9198.4 april 17, 2009 in voltage doubler configuration, the maximum v on is as given by equations 17, 18 and 19: for voltage tripler: v on output voltage is dete rmined by equation 19: negative charge pump design consideration the negative charge pump consists of an internal switcher m1, m2 which drives external steering diodes d2 and d3 via a pump capacitor (c12) to generate the negative v off supply. an internal comparator (a1) senses the feedback voltage on fbn and turns on m1 for a period up to half a clk period to maintain v (fbn) in regulated operation at 0.2v. external feedback resistor r6 is referenced to v ref . faults on v off which cause v fbn to rise to more than 0.4v, are detected by comparator (a2) and cause the fault detection system to start a fault ramp on c dly pin which will cause the chip to power down if present for more than the time tfd (see "electrical specification" section and also figure ?v on function diagram? on page 15). figure 16. v on function diagram vsup vsup vsup c1- pout fbp control c1+ c2- c2+ d3 d2 d1 m2 m4 m1 m3 m5 v ref 1.2mhz x2 mode x3 mode both external connections and components 0.9v c7 c8 c14 c21 r8 r9 c22 error fb v on_max(2x) 2v sup v diode ? () ? 2i out 2r onh r onl + ? () ? ? ? = (eq. 17) v on_max(3x) 3v sup v diode ? () ? 2i out 3r onh 2r onl ? + ? () ? ? ? = (eq. 18) v on v fbp 1 r 8 r 9 ------ - + ?? ?? ?? ? = (eq. 19) isl97650
16 fn9198.4 april 17, 2009 the maximum v off output voltage of a single stage charge pump is: r6 and r7 in the ?typical application diagram? on page 10 determine v off output voltage. improving charge pump noise immunity depending on pcb layout and environment, noise pick-up at the fbp and fbn inputs, which may degrade load regulation performance, can be reduced by the inclusion of capacitors across the feedback resistor s (e.g. in the application diagram, c21 and c22 for the positive charge pump). set r6 ? c20 = r7 ? c19 with c19 ~ 100pf. v on slice circuit the v on slice circuit functions as a three way multiplexer, switching the voltage on com between ground, drn and src, under control of the start- up sequence and the ctl pin. during the start-up sequence, com is held at ground via an ndmos fet, with ~1k impedance. once the start-up sequence has completed, ctl is enabled and acts as a multiplexer control such that if ctl is low, com connects to drn through a 30 internal mosfet, and if ctl is high, com connects to p out internally via a 5 mosfet. the slew rate of start-up of the switch control circuit is mainly restricted by the load capacitance at com pin as shown in equation 22: where v g is the supply voltage applied to drn or voltage at p out , which range from 0v to 36v. r i is the resistance between com and drn or p out including the internal mosfet r ds(on) , the trace resistance and the resistor inserted, r l is the load resistance of switch control circuit, and c l is the load capacitance of switch control circuit. in the ?typical application diagram? on page 10, r10, r11 and c15 give the bias to drn based on equation 23: r12 can be adjusted to adjust the slew rate. figure 17. negative charge pump block diagram fault 0.2v clk en vdd vsup fbn nout pgnd stop pwm control v ref r6 40k c20 820pf c19 100pf r7 328k v off (-8v) c13 470nf d2 d3 c12 220nf a2 0.4v a1 m1 m2 1.2mhz v off_max 2x () v sup ? v diode 2i out r on nout () hr on nout () l + () ? ? ++ = (eq. 20) v off v fbn 1 r7 r6 ------- - + ?? ?? v ref ? ? r7 r6 ------- - ?? ?? ? = (eq. 21) v t ------- - v g r i r l || () c l ------------------------------------ - = (eq. 22) v drn v on r 11 +avdd r 10 ? ? r 10 r 11 + -------------------------------------------------------------- - = (eq. 23) isl97650
17 fn9198.4 april 17, 2009 start-up sequence figure 18 shows a detailed start-up sequence waveform. for a successful power up, there should be 6 peaks at v cdly . when a fault is detected, the device will latch off until either en is toggled or the input supply is recycled. when the input voltage is higher than 3.85v, v ref turns on, as well as v logic if the enl is high. an internal current source starts to charge c cdly to an upper threshold using a fast ramp followed by a slow ramp. during the initial slow ramp, the device checks whether there is a fault condition. if no fault is found, c cdly is discharged after the first peak and v ref turns on. initially the boost is not enabled so a vdd rises to v in -v diode through the output diode. hence, there is a step at a vdd during this part of the st art-up sequence. if this step is not desirable, an external pmos fet can be used to figure 18. start-up sequence v cdly en v ref v boost v logic v off delayed v boost v on a vdd soft-start v off , delb on v on soft-start fault detected chip disabled normal operation fault present start-up sequence timed by c dly v ref , v logic on t ss t start-up t voff v in t von t von-slice v on slice note: not to scale isl97650
18 fn9198.4 april 17, 2009 delay the output until the boost is enabled internally. the delayed output appears at a vdd . a vdd soft-starts at the beginning of the third ramp. the soft-start ramp depends on the value of the c dly capacitor. for c dly of 220nf, the soft-start time is ~9.6ms. v off turns on at the start of the fourth peak. at the same time, delb gate goes low to turn on the external pmos to generate a delayed a vdd output. v on is enabled at the beginning of the sixth ramp. once the start-up sequence is complete, the voltage on the c dly capacitor remains at 1.15v until either a fault is detected or the en pin is disabl ed. if a fault is detected, the voltage on c dly rises to 2.4v at which point the chip is disabled until the power is cycled or enable is toggled. a vdd_delay generation using delb delb pin is an open drain internal n-fet output used to drive an external optional p-fet to provide a delayed a vdd supply which also has no initial pedistal voltage (see figure 14 and compare the a vdd and a vdd_delayed curves). when the part is enabled, the n-fet is held off until c dly reaches the 4th peak in the start-up sequence. during this period, the voltage potentia l of the source and gate of the external p-fet (m0 in application diagram) should be almost the same due to the presence of the resistor (r4) across the source and gate, hence m0 will be off. please note that the maximum leakage of delb in this period is 500na. to avoid any mis-trigger, the maximum value of r4 should be less than: where v gs(th)_min(m0) is the minimum value of gate threshold voltage of m0. after c dly reaches the 4th peak, the internal n-fet is turned-on and produces an in itial current output of idelb_on1 (~50a). this current allows the user to control the turn-on inrush current into the a vdd_delay supply capacitors by a suitable choice of c4. this capacitor can provide extra delay and also f ilter out any noise coupled into the gate of m0, avoiding spurious turn-on, however, c4 must not be so large that it prevents delb reaching 0.6v by the end of the start-up sequence on c dly , else a fault time-out ramp on c dly will start. a value of 22nf is typically required for c4. the 0.6v threshold is used by the chip's fault detection system and if v(delb) is still above 0.6v at the end of the power sequencing t hen a fault time-out ramp will be initiated on c dly . when the voltage at delb falls below ~0.6v, it's current is increased to idelb_on2 (~1.4ma) to firmly pull the delb voltage to ground. if the maximum v gs voltage of m0 is less than the a vdd voltage being used, then a resistor may be inserted between the delb pin and the gate of m0 such that it's potential divider action with r4 ensures the gate/source stays below vgs(m0)max. this additional resistor allows much larger values of c4 to be used, and hence longer a vdd delay, without affecting the faul t protection on delb. component selection for start-up sequencing and fault protection the c ref capacitor is typically set at 220nf and is required to stabilize the v ref output. the range of c ref is from 22nf to 1f and should not be more than five times the capacitor on cdel to ensure correct start-up operation. the cdel capacitor is typically 220nf and has a usable range from 47nf minimum to several microfarads - only limited by the leakage in the capacitor reaching a levels. cdel should be at least 1/5 of the value of c ref (see previous). note, with 220nf on cdel, the fault time-out will be typically 50ms. and the use of a larger/smaller value will vary this time proportionally (e.g. 1f will give a fault time- out period of typically 230ms). fault sequencing the isl97650 has advanced overall fault detection systems including over current protection (ocp) for both boost and buck converters, under voltage lockout protection (uvlp) and over-temperature protection. once the peak current flowing through the switching mosfet of the boost and buck converters triggers the current limit threshold, the pw m comparator will disable the output, cycle by cycle, until th e current is back to normal. the isl97650 detects each feedback voltage of a vdd , v on , v off and v logic . if any of the v on , v off or a vdd feedback is lower than the fault threshold, then a timed fault ramp will appear on cdel. if it completes, then v on , v off and a vdd will shut down, but v logic will stay on. if v logic feedback is lower than fault threshold, then all channels will switch off, and v in or enable needs recycling to turn them on again. an internal temperature sens or continuously monitors the die temperature. in the event that the die temperature exceeds the thermal trip point of +150c, the device will shut down. operation with die temper atures between +125c and +150c can be tolerated for short periods of time, however, in order to maximize the operating life of the ic, it is recommended that the effect ive continuous operating junction temperature of the di e should not exceed +125c. r 4_max v gs th () _min(m0) 500na ------------------------------------------- - < (eq. 24) isl97650
19 all intersil u.s. products are manufactured, asse mbled and tested utilizing iso9000 quality systems. intersil corporation?s quality certifications ca n be viewed at www.intersil.com/design/quality intersil products are sold by description only. intersil corpor ation reserves the right to make changes in circuit design, soft ware and/or specifications at any time without notice. accordingly, the reader is cautioned to verify that data sheets are current before placing orders. information furnishe d by intersil is believed to be accurate and reliable. however, no responsibility is assumed by intersil or its subsidiaries for its use; nor for any infringements of paten ts or other rights of third parties which may result from its use. no license is granted by implication or otherwise under any patent or patent rights of intersil or its subsidiari es. for information regarding intersil corporation and its products, see www.intersil.com fn9198.4 april 17, 2009 layout recommendation the device's performance including efficiency, output noise, transient response and control loop stability is dramatically affected by the pcb layout. pcb layout is critical, especially at high switching frequency. there are some general guidelines for layout: 1. place the external power components (the input capacitors, output capacitors, boost inductor and output diodes, etc.) in close proximity to the device. traces to these components should be kept as short and wide as possible to minimize parasitic inductance and resistance. 2. place v ref and v dc bypass capacitors close to the pins. 3. reduce the loop with large ac amplitudes and fast slew rate. 4. the feedback network should sense the output voltage directly from the point of load, and be as far away from lx node as possible. 5. the power ground (pgnd) and signal ground (sgnd) pins should be connected at only one point. 6. the exposed die plate, on the underneath of the package, should be soldered to an equivalent area of metal on the pcb. this contact area should have multiple via connections to the back of the pcb as well as connections to intermediate pcb layers, if available, to maximize thermal dissipation away from the ic. 7. to minimize the thermal resistance of the package when soldered to a multi-layer pcb, the amount of copper track and ground plane area connected to the exposed die plate should be maximized and spread out as far as possible from the ic. the bottom and top pcb areas especially should be maximized to allow thermal dissipation to the surrounding air. 8. minimize feedback input track lengths to avoid switching noise pick-up. a demo board is available to illustrate the proper layout implementation. isl97650
20 fn9198.4 april 17, 2009 isl97650 package outline drawing l36.6x6 36 lead thin quad flat no-lead plastic package rev 5, 08/08 bottom view side view typical recommended land pattern top view dimensioning and tolerancing conform to amsey14.5m-1994. dimension applies to the metallized terminal and is measured the configuration of the pin #1 identifier is optional, but must be between 0.15mm and 0.30mm from the terminal tip. tiebar shown (if present) is a non-functional feature. unless otherwise specified, tolerance : decimal 0.05 4. 5. 6. 3. 2. dimensions are in millimeters. 1. located within the zone indicated. the pin #1 indentifier may be either a mold or mark feature. c detail "x" 0 . 2 ref 0 . 05 max. 0 . 00 min. 5 6.00 a b 6.00 (4x) 0.15 6 pin 1 index area 28 pin #1 index area 36 32x 0.50 4.15 +0.10/-0.15 9 1 27 19 18 36x 0.55 0.10 10 6 4x 4.00 max 0.80 see detail "x" 0.08 0.10 c c c ( 5.65 ) ( 4.15) (36x 0.75) (36x .25) ( 32x 0.50) ( 5.65 ) ( 4x 4.00) exp. dap. ( 4.15) exp. dap. 0.10 36x 0.25 +0.05/-.07 a m c b 4

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